This application is a divisional of U.S. patent application Ser. No. 13/137,950, filed Sep. 22, 2011 (now U.S. Pat. No. 8,959,131), which claims priority of GB Application No. 1103020.2 filed Feb. 22, 2011, the entire contents of each of which are incorporated herein by reference.
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems supporting multiple number formats where it is desired to convert numbers between those formats.
It is known to provide data processing systems which support floating point numbers. Such floating point numbers may be represented in accordance with the IEEE 754 Standard. Such floating point numbers include a sign bit, an exponent field and a mantissa field. Different floating point number lengths are supported, such as 16-bit floating point numbers, 32-bit floating point numbers and 64-bit floating point numbers. In some forms of desired processing it is necessary to convert an operand from one floating number point format to a narrower number floating point format. When the mantissa field of a floating point number is reduced in size, it is necessary to perform rounding in relation to the portion of the mantissa field which is being lost. Various rounding modes are known and include round-to-nearest ties to even. An problem that can arise is the rounding is performed in more than one stage, i.e. first rounding to a mantissa of an intermediate length and then rounding to the final shorter mantissa. In this situation it is possible that a different mantissa will result compared to if the mantissa field was subject to one rounding operation and went directly from its initial field length to its final field length. This type of error may be termed a double rounding error.